A number of circuits are provided with redundant elements, typically for the purpose of replacing a normally-used element which is defective. For example, a memory array may include a plurality of normally-used columns of memory cells plus one or more redundant columns. When a normally-used column is found to be defective, it is desired to discontinue use of the defective column and initiate use of a redundant column. Devices have previously been provided for substituting a redundant row or block of memory cells for a faulty row or block. However, previous devices have had certain deficiencies, particularly in the context of apparatus that must operate rapidly. U.S. Pat. No. 4,654,830 issued Mar. 31, 1987 to Chua et al. discloses a device in which the substitution involves opening a plurality of fuses in a defective row or block and also opening a plurality of fuses in the portion of the circuit which addresses the redundant row or block. There are, however, yield penalties associated with needing to open a plurality of fuses. For example, if in a typical device, a given percentage of fuses can be expected to be defective (e.g., not blowable) then the probability of being unable to substitute a redundant element is larger if a larger number of fuses needs to be opened than if a smaller number of fuses needs to be opened.
Furthermore, certain previous devices required the routing of signals over relatively long distances, such as routing a signal from a redundant element past a number of non-defective normally used elements to achieve the desired functionality.
Furthermore, some previous devices required a large number of logic gates in the data path in order to provide the desired functionality. Each logic element in the data path or critical path adds more delay to the propagating signal which cannot be tolerated in high-speed circuits.
Accordingly, it would be useful to provide a redundancy element substitution circuit which reduces or minimizes the yield penalties associated with requiring the opening of large number of fuses, the area penalties associated with routing signals over a long distance and the timing delay penalties associated with placing a large number of logic gates in the critical path.